In synchronous data communication systems a problem exists to maintain the clock at the receiver in phase synchronization with the clock at the transmitter. Synchronization is needed to enable clock signals at the receiver to coincide with the center of the received data pulses, thus assuring that data bits are not added, lost or misinterpreted during data transmission. In addition to keeping the receive clock in exact synchronization with the transmit clock, there is a need to control the instantaneous phase jitter of the receive clock with respect to the long term average clock frequency. Typically, this maximum phase jitter may be of the order of 0.5 percent of a single clock period.
One prior art technique for synchronizing the receiver clock to the transmitter clock includes sending the clock information as part of the transmitted data. At the receiver location the clock information is extracted from the received data. The transmission of clock information as part of the data requires that the data be transmitted continuously over the facility to the receiver. However, when data is transmitted in a non-continuous bursty manner or is multiplexed together with other signals, the clock information is not easily derived from the transmitted data.
In these bursty or multiplex data transmission systems the clock information is usually transmitted as separate data over the facility. When a common reference clock is available at the transmitter and receiver differential clock information is sent relative to this reference clock. Typically, the differential clock information is transmitted by the transmitter periodically, usually determined by either a time interval or by the number of data bits transmitted. The interval between clock information transmissions is usually determined by the required system clock tolerance and the stability of the transmitter and receiver clocks. The received differential clock information is combined with the facility reference clock to synchronize the receiver clock within the specified system clock tolerance of the transmitter clock. Thus, the transmitted differential clock information must contain enough data bits of information to enable a resolution of clock phase to within the system clock jitter tolerance.
For example, if the system clock jitter tolerance is .+-.0.5 percent, then the transmitted differential clock information must contain at least 8 bits (2.sup.8 =256 steps or about 0.4 percent/step) to specify the receiver clock phase within .+-.0.5 percent of the transmitter clock phase. Moreover, the relative drift of the transmitter and receiver clocks often determines how frequently the receiver clock must be resynchronized. Thus, for example, if transmitter and receiver clocks have a relative drift of 125 parts per million (PPM) per cycle (or per bit), then to maintain a system clock jitter tolerance of .+-.0.5 percent requires sending clock information every 40 data bits 0.5 percent/125 PPM. In such a system 8 bits of differential clock information must be sent after each 40 data bits to maintain the receiver clock with the .+-.0.5 percent tolerance of the transmitter clock. Thus undesirably, transmission of the clock information requires almost 17 percent (8 bits out of 48 total) of all the data sent (8 bits out of 48 total) by the transmitter.
If a synchronous data communication system is to be efficient, the utilization of valuable data channel capacity for clock information transmission should be minimized. However, in systems which do not have the added capacity required for transmitting the clock information data, maintaining the receiver clock within the specified tolerance of the transmitter clock may not be possible using the above method.